Automated fault insertion and load application to a device-under-test enables repeatable design validation iterations.
An elegant and cost-effective method is through Digalog Systems CableFreeATE™.
- 0.1" Discrete Header 64 SPST Reed Relay
Design Verification platform for ASICs, firmware, and embedded systems, incorporates visions system and environmental chamber for complete end to end solution.
- Easy to use manually or automatically
- Graphical Test pattern editor
- Environmental chamber control
- Python and MATLAB script integration
- Various levels: code testing to system level
- Allows for model-based testing and simulation
- Vision system or frame-grabber for displays
- Vehicle communications networks such as CAN, LIN
- Automation networks: Modbus, Ethernet/IP
- Your core IP on Windows, Real-time, or FPGA devices